VR Goggles

Video Codec IPs
Supporting 4K Resolution

WAVE520C

WAVE520C is a HEVC/H.265 codec IP core that supports 4K60fps video encoding and/or decoding with HEVC/H.265 in real-time. WAVE520C is Chips&Media's 2nd generation video IP, which achieves the best encoding quality at high resolution and frame rate. It features highly enhanced performance and efficient use of system bandwidth with a frame compression algorithm for high-end multimedia SoCs. WAVE520C is able to encode and/or decode any resolution up to 8192x4096 and guarantees real-time performance for encoding/decoding 4K60fps @500MHz. In addition, by sharing common blocks of the HEVC codec, the IP architecture becomes streamlined with minimum logics and memories fitting into small-sized SoCs. Thereby SoCs using WAVE520C are perfectly suited for applications requiring high performance with very low power consumption.

Performance

  • Encoder:​

    • HEVC/H.265 Main/Main10 Profile, Main Still/Main10 Still Profile @L5.1; 3840x2160 @60fps 500MHz​

  • Decoder:

    • HEVC/H.265 Main/Main10 Profile @L5.1 High-tier; 3840x2160 @60fps 450MHz

Interface

  • 32-bit AMBA2 APB bus​

  • 128-bit AMBA3 AXI buses

  • Primary AXI interface and an optional secondary AXI interface

Features

  • Rotation and mirroring​

  • Bit-depth and chroma format conversion

  • 3DNR

  • Low delay encoding/decoding

  • Latency tolerance

  • Configurable IP

  • Programmability

  • Low power consumption

  • Frame-based processing

  • Handling multi-instances

WAVE521C

WAVE521C is a 4K multi-format codec IP to support both HEVC/H.265 and AVC/H.264 video formats. The IP core provides high-performance encode and decode capability up to 4K60fps with a single-core architecture and an optimized silicon area for 4K Ultra-HD applications such as security IP-cameras, wearable cameras, drone cameras, automotive, NVR, and more. WAVE521C is able to encode and/or decode any resolution up to 8192x4096 and guarantees real-time performance for encoding/decoding 4K60fps @500MHz. In addition, by sharing common blocks of the HEVC/H.265 and AVC/H.264 codec, the IP architecture becomes streamlined with minimum logics and memories fitting into small-sized SoCs. Thereby SoCs using WAVE521C are perfectly suited for applications requiring high performance with very low power consumption.

Performance

  • Encoder:​

    • HEVC/H.265 Main/Main10 Profile, Main Still/Main10 Still Profile @L5.2​

    • AVC/H.264 BP/CBP/MP/HP/HP/HP10 @L6.0

  • Decoder:

    • HEVC/H.265 Main/Main10 Profile @L5.1 High-tier​​

    • AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2

Interface

  • AMBA3 32bit APB interface for communication with host CPU​​

  • AMBA3 128bit AXI interface for data transmission

  • Primary AXI interface and an optional secondary AXI interface

Features

  • Low delay​​

  • Low power consumption

  • Configurable IP

  • Latency tolerance

  • Programmability

  • Multi-instances

  • 3DNR

  • Frame buffer compression (CFrame)

  • Down-scaler

  • Rotation/Mirroring

  • Bit-depth and chroma format conversion

  • Burst Write Back

  • Map converter

 
 

WAVE521CL

WAVE521CL is a low-cost 4K codec IP to support both HEVC/H.265 and AVC/H.264 video formats. The IP core provides high-performance encode and decode capability up to 4K@60fps with a single-core architecture and an optimized silicon area for 4K Ultra-HD applications. WAVE521CL is able to encode and/or decode any resolution up to 8192x4096 and guarantees real-time performance for encoding/decoding 4K60fps @500MHz and is highly optimized for memory bandwidth loading and excellent power management.

Performance

  • Encoder (3840x2160 @60fps)​

    • HEVC/H.265 Main and Main Still Picture Profile @L5.1 High-tier​​

    • AVC/H.264 Baseline/Constrained Baseline/Main/High Profiles Level@L5.2

  • Decoder (3840x2160 @60fps)

    • HEVC/H.265 Main and Main Still Picture Profile @L5.1 High-tier​​

    • AVC/H.264 Baseline/Constrained Baseline/Main/High Profiles Level@L5.2

Interface

  • 32-bit AMBA2 APB bus​​

  • 128-bit AMBA3 AXI bus

  • Primary AXI interface and an optional secondary AXI interface

Features

  • Low power consumption​

  • Latency tolerance

  • Configurable IP

  • WPP encoding with a single slice

  • Rotation and mirroring

  • Handling multi-instances

  • Programmability

  • 3DNR

  • Frame-based processing

  • AIR for error resilience

  • Frame buffer compression (CFrame)

  • Burst Write Back

  • Down-scaler

  • Map converter

 

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